The present invention relates to a manufacturing method for a resin sealed semiconductor device, for example, applicable to a molding of a hybrid IC substrate with a resin to seal the entire body thereof. Especially, the present invention relates to a manufacturing method for eliminating the generation of undesirable voids in the resin during a molding process of the resin sealed semiconductor device.
In general, a hybrid IC substrate has an excellent durability against high voltages which cannot be handled by a silicon semiconductor element, as well as robustness against noises. These characteristics of the hybrid IC substrate are suitable for a semiconductor device installed in an automotive vehicle. In many cases, the hybrid IC substrate is incorporated in a control unit for a power actuator and is usually combined with a power transistor.
To realize an easy installation of the control unit to the power actuator, downsizing the control unit is necessarily required. Conventionally, a semiconductor device including a hybrid IC substrate is manufactured by using a resin casing. A semiconductor device is assembled beforehand in the resin casing. Liquefied resin is injected in the resin casing and hardened for sealing the semiconductor device with the resin. However, according to such a conventional method of using a resin casing is disadvantageous in that the downsizing of the mold product is not satisfactorily realized because the resin casing needs to be enlarged enough to assure a smooth flow of the liquefied resin.
As other manufacturing method not relying on a special molding casing, there is a mold sealing method which is conventionally employed for sealing a silicon semiconductor. FIG. 11 shows a resin sealed semiconductor device manufactured according to the conventional mold sealing method. A lead frame base 30 is assembled with a hybrid IC substrate 31 and a power transistor 32 mounted on an upper surface thereof. The assembled lead frame member is supported in a cavity defined between the molding dies. Then, a resin 33 is injected in the cavity to entirely seal the assembled body with the resin 33. According to this mold sealing method, the downsizing is realized satisfactorily due to no provision of the special molding casing. However, compared with the silicon semiconductor element, the hybrid IC substrate 31 is large in size. Furthermore, the longitudinal length of the lead frame base 30 is large because the hybrid IC substrate 31 and the power transistor 32 need to be molded together on this lead frame base 30.
Moreover, there is a necessity of radiating the heat generated from the power transistor 32 to the outside through the lead frame base 30 and the lower molding resin layer. Thus, to improve the heat radiation property, the thickness of the lower molding resin layer needs to be reduced adequately. On the other hand, a chip 34 is mounted on the hybrid IC substrate 31. The power transistor 32 and the hybrid IC substrate 31 and the inner frames 35 are connected by wires 36 and 37. To provide a sufficient space for these components mounted on the lead frame base 30, the thickness of the upper molding resin layer needs to be increased adequately. In other words, the upper and lower molding resin layers are not uniform in their thicknesses.
The above-described complicated, elongated and unbalanced structural features of the semiconductor device possibly causes a speed difference between the resin flows in a molding operation when the injected resin is separated into the upper and lower regions of the molding cavity and advance in the longitudinal direction toward an air vent. More specifically, one resin flow advances in the upper region of the molding cavity and is decelerated by the obstacles, such as the hybrid IC substrate 31 and the power transistor 32, which protrude upward from the lead frame base 30. On the other hand, the other resin flow advances in the lower region of the molding cavity and smoothly moves along the flush bottom surface of the lead frame base 30.
FIG. 12 shows another conventional resin sealed semiconductor device according to which the bottom of the lead frame base 30 is not resin molded. This arrangement is advantageous in improving the heat radiation property, however is not reliable in the durability against repetitive thermal cycles because there is a significant thermal expansion difference between the molded resin 33 and the lead frame base 30. Thus, the molded resin 33 is possibly peeled off the surface of the lead frame base 30. The sensitive circuit components, such as chip 34 mounted on the hybrid IC substrate 31, will be damaged by moisture or dusts entering from the outside through a clearance formed at the peeled portion.
FIG. 13 shows another conventional resin sealed semiconductor device according to which the upper side of the hybrid IC 31 is coated beforehand with a thick resin coating material 38. According to this arrangement, the speed of the resin flow advancing in the upper region of the cavity can be decelerated adequately so as to eliminate the speed difference between the upper and lower resin flows. However, according to this structure, the wires 36 and 37 are subjected to and may be broken by a thermal stress derived from a thermal expansion coefficient difference between the coating material 38 and the molding material 33.
In view of the foregoing, it is definitely necessary to solve the problems arisen during a molding operation of a resin molded semiconductor device when the upper and lower resin layers are not uniform in their thicknesses. More specifically, there is a possibility that a significant amount of voids may remain in the cavity due to a flow speed difference between the upper and lower resin flows.
To eliminate the generation of such undesirable voids, Unexamined Japanese Patent Application No. 1-158756, published in 1989, proposes to provide a gate at a lower position and restricts the upward resin flow by a protrusion of a lead frame. Unexamined Japanese Patent Application No. 6-104364, published in 1994, proposes to provide a protrusion on a lead frame to equalize the upper and lower resin flow speeds. However, these arrangements are disadvantageous in that an overall size of the molded product becomes large due to the provision of the special protrusions.
Furthermore, Unexamined Japanese Patent Application No. 1-291434, published in 1989, proposes to use a slidable mold in an upper die in the vicinity of a gate to restrict the resin flow by controlling the position of the slidable mold. However, this arrangement is disadvantageous in that the slidable mold may interfere with a chip or other components mounted on a hybrid IC substrate.